In an EEPROM type memory system using non-volatile memory transistor devices, the memory transistor of a memory cell into which a logic "1" data has been written has a certain first level of threshold voltage. When the bit of data thus written into the memory cell is erased electrically so that a logic "0" data is "written " into the memory cell including the particular transistor, the threshold voltage of the memory transistor shifts to a second threshold voltage which is typically higher than the first threshold voltage. During read mode of operation, a certain readout voltage lower than the first threshold voltage and higher than the second threshold voltage is applied to the control gate of the memory transistor thus storing a logic "1" or "0" data from a gate control circuit predominant over all of the memory cells forming the memory array. In response to the readout voltage, the transistor becomes conductive if the content of the memory cell including the particular transistor is of logic "1" value or non-conductive if the content of the memory cell is of logic "0" value. The conductive or non-conductive state of the memory transistor is detected by an associated sense amplifier so that either a logic "1" bit of data or a logic " 0" bit of data is output to an input/output interface as is customary.
In a known EEPROM type memory system of this nature, the readout voltage to be supplied from the gate control circuit is typically selected at ground level with the aforesaid first and second threshold voltages selected to be equal in magnitude to each other with respect to the ground level. As will be discussed in more detail, the use of a voltage of the ground level as the readout voltage however results in reduction in the current to flow through the memory transistor storing a logic "1" data when the transistor is selected during the read mode of operation. The small current through the transistor is ordinarily insufficient for enabling the associated sense amplifier to respond fast and properly to the conductive, logic "1" state of the transistor. The operation time required for a sense amplifier shares considerably in the total operation time of an EEPROM system as well known in the art and, for this reason, it is important to enable the sense amplifier to operate faster for achieving a higher speed of operation of the system as a whole. Thus, a prior-art gate control circuit of the described nature has a drawback in that the control circuit is not compatible in performance with an EEPROM system which is essentially required to operate at high speeds.
Another problem encountered in an EEPROM system is the degradation of the performance quality of the memory transistors as caused by the repeated write-erase cycles which the transistors will experience during use of the system. As will be discussed in detail, a prior-art gate control circuit of the described nature further has a drawback in that the circuit has not such a margin that is broad enough to compensate for such degradation of the performance quality of the memory transistors.
It is, accordingly, an important object of the present invention to provide an improved EEPROM memory system using non-volatile memory devices and featuring a gate control circuit adapted to produce an increased current through a memory transistor storing a logic "1" bit of data when the particular memory transistor is selected during read mode of operation.
It is another important object of the present invention to provide an improved EEPROM memory system using non-volatile memory devices and incorporating a gate control circuit which is relatively simple in construction and which provides a margin broad enough to compensate for the degradation of the performance quality of the memory transistors as caused when the transistors have repeated a number of write-erase cycles.